منابع مشابه
Low-power Full Adder array-based Multiplier with Domino Logic
ABSTRACT : A circuit design for a low-power full adder array-based multiplier in domino logic is proposed. It is based on Wallace tree technique. Clocked architecture results in lower power dissipation and improvements in power-delay product. The proposed technique is general and can be used in all domino logic circuit designs. Higher order multipliers like 16x16, 32x32 may also be implemented ...
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A core operation in actual circuits, especially in digital signal processing algorithms, is multiplication. Often, the computational performance of a DSP system is limited by its multiplication performance [Pet95]. The implementation of multiplier modules into FPGAs is crucial in terms of area, speed and pin limitation. In many cases, even small multiplier modules will exceed the capacity of on...
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ژورنال
عنوان ژورنال: IOSR Journal of Engineering
سال: 2012
ISSN: 2278-8719,2250-3021
DOI: 10.9790/3021-0204923927